Phase-locked loops are integral components of clock generation circuits. A phase-locked loop (PLL) circuit is a feedback system that generates an output signal whose phase is constant relative to the phase of an input reference signal. In addition to synchronizing signals, a phase-locked loop can generate a frequency that is a multiple of the input frequency.
For example, shown in FIG. 1 is a typical PLL circuit 100. The PLL 100 includes a phase detector (PFD) 102, charge pump 104, loop filter 106, and VCO 108. The phase detector 102 compares the input signal and a feedback signal. The PFD 102 detects the difference in phase and frequency between the reference signal ref(t) and a feedback signal div(t) and generates an up(t) or down(t) control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO 108 needs to operate at a higher or lower frequency, respectively.
The PFD 102 outputs these “up” and “down” signals to the charge pump 104. If the charge pump 104 receives an up signal, current is driven into the loop filter 106. Conversely, if it receives a down signal, current is drawn from the loop filter 106.
The loop filter 106 converts these signals to a control voltage Vtune(t) that is used to bias the VCO 108. Based on the control voltage, the VCO 108 oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD 102 produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO 108 stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter 106 filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.
In some implementations, a frequency divider 110 is provided in the feedback path. Negative feedback forces the error signal output from the phase detector 102 to approach zero. At this point, the feedback divider output 110 and the reference frequency are in phase and frequency lock, i.e., aligned, the PLL is considered locked.
An on-chip implementation of a charge pump PLL is problematic, largely due to the loop filter. That is, the area occupied by the loop filter, and the power consumed by the loop filter, tends to be relatively large. Consequently, typical implementations of PLLs provide off-chip loop filters. For example, low frequency PLLs typically need an off-chip capacitor in the range of nF.